Schematically shown in FIG. 1 is a plot of an idealized clock signal 100. The clock signal 100 is presented, by way of example, as an electrical voltage V varying as a function of time t. More generally, the clock signal is the time-dependence of a physical quantity. For example, the clock signal could be provided optically by a variation of an intensity of light. The signal V(t) shown here is a regular succession of high and low values, V0 and V1, respectively. The low values last a time T0, the high values last a time T1. In the example shown, T0 and T1 are equal, but other ratios configurations are also commonly used in the art. Transitions from the low value V0 to the high value V1 are referred to as a rising edges. In the example, rising edges occur at equidistant times t1, t3, and t5. Transitions from the high value V1 to the low value V0 are termed falling edges. In the example, falling edges occur at equidistant times t0, t2, and t4. Rising edges and falling edges are summarily referred to as clock edges.
Any synchronous circuit relies on the presence of a clock signal similar to the one illustrated in the Figure. Operations to be performed by the components of the circuit are triggered by clock edges, for example, only by rising edges, or only by falling edges, or by both falling and rising edges. After an operation has been performed, the component waits for the next edge before executing the next operation. The various components can thus be synchronized. Any component thus controlled by the clock signal is said to be clocked by the clock signal.
Usually a problem arises if an edge in the clock signal is generated early, late, or unexpectedly. Less critical are cases, where the interval between two subsequent edges is longer than usual, for example, due to a stall of the device generating the clock signal. In contrast, functional errors may occur if either T0 or T1 (or both) are shorter than expected. These are typical examples of clock glitches. In these cases, components of the synchronous circuit may still be busy with an operation when receiving the edge and therefore the edge will either not trigger an action or trigger a faulty action. In FIG. 2, the time T0′ is shorter than expected. In FIG. 3, the time T1′ is shorter than expected.
Clock glitches are a prominent root cause for many functional errors of an electronic device. In case of devices targeted for safety related applications the detection of clock glitches is of special importance, since many common cause failures are either generated by clock glitches or will also result in clock glitches.